Probe card partition scheme
US8836363B2 · kind B2 · utility
4Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2011 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | May 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31908
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of probe card partitioning for testing an integrated circuit die includes providing a first probe card partition layout having a first number of distinct sections. Each distinct section uses a distinct probe card for testing. The first probe card partition layout is repartitioned into a second probe card partition layout having a second number of distinct sections. The second number is less than the first number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.