Patent · US Active

Method for testing integrated circuits with hysteresis

US8836366B2 · kind B2 · utility

0Cited by

8References

25Claims

0Family size

Assignee

Apple Inc. · US

Inventors

Anh-Tuan Hoang · Plymouth, US
Brian S. Park · San Jose, US
Patrick D. McNamara · San Francisco, US

Key dates

Filing date	Apr 24, 2012
Grant date	Sep 16, 2014
Priority date	—
Expiry date	Dec 6, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/3163
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A system and method for testing circuits. A generated input voltage waveform for a first phase of a test may use transitions with a voltage swing between expected low and high trigger points for an integrated circuit (IC) with hysteresis. A generated input voltage waveform for a second phase of the test may use transitions with a voltage swing between the expected low trigger point and a high sub-threshold value. The high sub-threshold value may be a tolerable voltage difference below the expected high trigger point. A generated input voltage waveform for a third phase of the test may use transitions with a voltage swing between the expected high trigger point and a low sub-threshold value. The low sub-threshold value may be a tolerable voltage difference above the expected low trigger point. The expected trigger points and sub-threshold values may be found from earlier characterization studies for the IC.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.