Voltage level shifter
US8836406B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 9, 2014 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Feb 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter includes a latch supplied at a first voltage VDD1. First and second switches are connected in series with first and second latches and are cross-coupled to maintain the state of the latches during a stability period. A controller responds to a change of state of an input signal at a voltage different from the first voltage at an end of the stability period to deactivate both the first and second switches, to cause third and fourth switches to deactivate both the first and second latches during a transition period, and subsequently to change the state of the latch and maintain the changed state during the subsequent stability period. This avoids undesirable compromise between current consumption and transfer delay, as in a conventional level shifter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.