N-bit rom cell
US8837192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2012 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Nov 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/165
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Among other things, an n-bit ROM cell, such as a twin-bit ROM cell, and techniques for addressing one or more ROM cell portions of the n-bit ROM cell are provided. A twin-bit ROM cell comprises a first ROM cell portion adjacent to or substantially contiguous with a second ROM cell portion. The first ROM cell portion is associated with a first data bit value. The second ROM cell portion is associated with a second data bit value distinct from the first data bit value. Because the first ROM cell portion is adjacent to the second ROM cell portion, OD-to-OD spacing between the twin-bit ROM cell and an adjacent twin-bit ROM cell is increased to provide, for example, improved isolation, cell current, ROM speed, and VCCmin performance in comparison with single-bit ROM cells, while maintaining a substantially similar to pitch as the single-bit ROM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.