Semiconductor device with low voltage programming/erasing operation
US8837251B2 · kind B2 · utility
2Cited by
14References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 5, 2009 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Nov 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.