Methods and apparatus for compressing partial products during a fused multiply-and-accumulate (FMAC) operation on operands having a packed-single-precision format
US8838664B2 · kind B2 · utility
2Cited by
8References
26Claims
0Family size
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Key dates
| Filing date | Jun 29, 2011 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Feb 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.