Specifying circuit level connectivity during circuit design synthesis
US8839162B2 · kind B2 · utility
58Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2010 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Jul 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.