Method and system allowing for semiconductor design rule optimization

US8839177B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Mark D. Aubel · Saint Johnsbury Center, US
• Jeanne P. Bickford · South Burlington, US
• Howard S. Landis · Underhill, US
• Michael Ross · Vandalia, US
• Mark S. Styduhar · South Burlington, US
• Charles H. Windisch, Jr. · South Burlington, US

Key dates

• Filing date: Aug 22, 2013
• Grant date: Sep 16, 2014
• Expiry date: Aug 22, 2033

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P90/02
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Disclosed are integrated circuit design systems and methods, wherein selected functional library elements are placed in a layout to meet product specifications and selected hybrid fill-placeable library elements are placed in that same layout to meet at least one feature density rule. Each hybrid fill-placeable library element comprises fill shapes corresponding to specific features subject to a density rule and a marker shape that provides an instruction to ignore any density rule violations within that element for purposes of design rule checking. Placement of the hybrid fill-placeable library elements is performed to balance out density rule violations in functional library elements elsewhere in the layout, thereby avoiding the need for post-processing of the completed IC design to add fill shapes. Optionally, each hybrid fill-placeable library element comprises different fill shapes at different levels and corresponding to different features so that it can be employed to meet multiple different density rules.