High electron mobility transistor and method of forming the same
US8841703B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2011 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Dec 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/854
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.