Pseudo self aligned radhard MOSFET and process of manufacture

US8841718B2 · kind B2 · utility

Assignee

• Microsemi Corporation · US

Inventors

• Dumitru Sdrulla · Bend, US
• Marc H. Vandenberg · Bend, US
• Eric Karlsson · Napa, US

Key dates

• Filing date: Jan 15, 2013
• Grant date: Sep 23, 2014
• Expiry date: Feb 24, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are “self aligned” to a “Sacrificial Poly” layer, which later on is removed, preparing the wafers for a “late gate” oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET.