Semiconductor device comprising a capacitor and an electrical connection via and fabrication method
US8841748B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2011 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Oct 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16145
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.