Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method
US8841749B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 17, 2011 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Aug 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/14181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.