Multi-layer interconnect structure for stacked dies
US8841773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2012 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Sep 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.