Automated control of opening and closing of synchronous dynamic random access memory rows
US8842480B2 · kind B2 · utility
10Cited by
17References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2012 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus including a protocol engine and a built-in self test (BIST) engine. The built-in self test (BIST) engine is coupled to the protocol engine. The built-in self test (BIST) engine may be configured to directly control when to open and close rows of a synchronous dynamic random access memory (SDRAM) during double data rate (DDR) operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.