Dynamically calibrated DDR memory controller
US8843778B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2013 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Sep 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.