Semiconductor package having buried post in encapsulant and method of manufacturing the same
US8846446B2 · kind B2 · utility
0Cited by
13References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2011 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Sep 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.