Gate structure for semiconductor device
US8847293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2012 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | May 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.