Pillars for vertical transistors
US8847298B2 · kind B2 · utility
8Cited by
86References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 13, 2013 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Dec 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.