Power device integration on a common substrate
US8847310B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 3, 2014 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Jun 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
A MOSFET includes an active region formed on an SOI substrate. A buried well is formed in the active region. A drain region having the first conductivity type is formed in the active region and spaced laterally from a source region and the buried well. A body region is formed in the active region between the source and drain regions on the buried well, and a drift region is formed in the active region between the drain and body regions on at least a portion of the buried well. A shielding structure is formed proximate the upper surface of the active region, overlapping a gate. During conduction, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes the drift region. The MOSFET is configured to sustain a linear mode of operation of an inversion channel formed under the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.