Semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure
US8847401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2012 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Oct 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure. The structure comprises a semiconductor device (e.g., a two-terminal device, such as a PN junction diode or Schottky diode, or a three-terminal device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), etc.) and a dielectric layer that covers the semiconductor device. A contact extends vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer is positioned on the contact sidewall and incorporates an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.