Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system
US8848414B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2012 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Feb 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.