Nonvolatile semiconductor memory device using write pulses with different voltage gradients
US8848447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2011 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Dec 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.