Memory cell having flexible read/write assist and method of using
US8848461B2 · kind B2 · utility
10Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2012 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Mar 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes at least one memory cell die. The at least one memory cell die includes a data storage unit. The at least one memory cell die includes at least one read assist enabling unit electrically connected to the data storage unit. The at least one read assist enabling unit configured to lower a voltage of a word line. The memory cell die also includes at least one write assist enabling unit electrically connected to the data storage unit. The at least one write assist enabling unit configured to supply a negative voltage to at least one of a bit line or a bit line bar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.