Load pair disjoint facility and instruction therefore
US8850166B2 · kind B2 · utility
38Cited by
20References
17Claims
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Key dates
| Filing date | Feb 18, 2010 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Nov 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.