Inter-processor failure detection and recovery
US8850262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2010 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Dec 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.