Timothy J. Van Patten
16Patents
3h-index
8Co-inventors
45Inventor score
Filing activity: Oct 4, 2010 → Aug 29, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8850262B2 | Inter-processor failure detection and recovery | Physics | 15 | Active |
| US9075720B2 | Locking a cache line for write operations on a bus | Physics | 4 | Active |
| US9377952B2 | Input/output port rotation in a storage area network device | Physics | 3 | Active |
| US8825915B2 | Input/output port rotation in a storage area network device | Physics | 3 | Active |
| US8904053B2 | Input/output port rotation in a storage area network device | Physics | 3 | Active |
| US9946670B2 | Determining when to throttle interrupts to limit interrupt processing to an interrupt processing time period | Physics | 2 | Active |
| US9164935B2 | Determining when to throttle interrupts to limit interrupt processing to an interrupt processing time period | Physics | 2 | Active |
| US9858223B2 | Input/output port rotation in a storage area network device | Physics | 1 | Active |
| US9436607B2 | Locking a cache line for write operations on a bus | Physics | 1 | Active |
| US10049050B2 | Locking a cache line for write operations on a bus | Physics | 1 | Active |
| US10901929B2 | Input/output port rotation in a storage area network device | Physics | 0 | Active |
| US10467164B2 | Input/output port rotation in a storage area network device | Physics | 0 | Active |
| US10331568B2 | Locking a cache line for write operations on a bus | Physics | 0 | Active |
| US8935511B2 | Determining processor offsets to synchronize processor time values | Physics | 0 | Active |
| US9811336B2 | Determining processor offsets to synchronize processor time values | Physics | 0 | Active |
| US8904058B2 | Selecting direct memory access engines in an adaptor input/output (I/O) requests received at the adaptor | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.