Method for stressing a thin pattern and transistor fabrication method incorporating said method

US8853023B2 · kind B2 · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Simeon Morvan · Dresden, DE
• Francois Andrieu · Meylan, FR
• Jean-Charles Barbe · Seyssinet-Pariset, FR

Key dates

• Filing date: Jan 29, 2013
• Grant date: Oct 7, 2014
• Expiry date: Mar 21, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/798
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for stressing a pattern having a pattern surface, in a layer of semiconductive material that can be silicon on the surface of a stack of layers generated on the surface of a substrate, said stack comprising at least one stress layer of alloy SixGey with x and y being molar fractions, and a buried layer of silicon oxide, comprises: etching at the periphery of a surface of dimensions greater than said pattern surface, of the buried layer of silicon oxide and layer of alloy SixGey over a part of the depth of said layer of alloy; the buried layer of silicon oxide being situated between said layer of semiconductive material and said stress layer of alloy SixGey. In a transistor structure, etching at the periphery of said surface obtains a pattern thus defined having dimensions greater than the area of interest situated under the gate of the transistor.