Defect reduction for formation of epitaxial layer in source and drain regions
US8853039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2013 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jan 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth. The mechanisms include controlled etch of a native oxide layer on the surfaces of recesses to reduce creation of particles, and pre-CDE etch to remove particles from surface. The mechanisms also include reduced etch/deposition ratio(s) of initial CDE unit cycle(s) of CDE process to reduce the effect of residual particles on the formation of the epitaxially grown silicon-containing layer. With the application of one or more of the mechanisms, the quality of the epitaxial layer is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.