Manufacturing method of circuit structure
US8853102B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2013 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Aug 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0338
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. The metal layer and the surface passivation layer are dipped into a modifier, and the modifier is selectively absorbed and attached to the surface passivation layer, so as to form a covering layer. The covering layer has a plurality of nanoparticles and covers the surface passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.