Integrated circuit within semiconductor chip including cross-coupled transistor configuration
US8853794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2014 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Apr 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/987
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and a conductive interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.