High-K metal gate device
US8853796B2 · kind B2 · utility
0Cited by
4References
26Claims
0Family size
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Key dates
| Filing date | May 19, 2011 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jun 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.