Bump structures
US8853853B2 · kind B2 · utility
21Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2011 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Dec 17, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24479
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The embodiments of bump and bump-on-trace (BOT) structures provide bumps with recess regions for reflowed solder to fill. The recess regions are placed in areas of the bumps where reflow solder is most likely to protrude. The recess regions reduce the risk of bump to trace shorting. As a result, yield can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.