Patent · US Active

Timer unit, system, computer program product and method for testing a logic circuit

US8854049B2 · kind B2 · utility

3Cited by
10References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 25, 2007
Grant dateOct 7, 2014
Priority date
Expiry dateJan 3, 2031

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/31727
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit. The system has a mode control unit containing a set of instructions which is executable by the logic circuit, for switching the logic circuit from and to a test mode in which a part of the logic circuit can be subjected to a selected test by executing a selected test routine.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.