Scan compression architecture with bypassable scan chains for low test mode power
US8856601B2 · kind B2 · utility
2Cited by
10References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2010 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Feb 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.