Device and method for testing a circuit to be tested
US8856629B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2012 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Oct 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v′)) based on a coded binary word (v′). The error syndrome bit sequence (s(v′)) indicates whether the coded binary word (v′) is a code word of an error correction code (C) used for coding the coded binary word (v′). The test sequence provider provides a test bit sequence (Ti) of the circuit that is different than the error syndrome bit sequence (s(v′)), if the error syndrome bit sequence (s(v′)) indicates that the coded binary word (v′) is a code word of the error correction code (C). The evaluation circuit detects an erroneous processing of the test bit sequence (Ti) by the circuit based on a test output signal (R(Ti)′)—caused by the test bit sequence (Ti)—of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.