System and method for metastability verification of circuits of an integrated circuit
US8856706B2 · kind B2 · utility
6Cited by
21References
26Claims
0Family size
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Key dates
| Filing date | May 6, 2013 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | May 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.