Optimized flip-flop device with standard and high threshold voltage MOS devices
US8856712B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2012 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Oct 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop operating with standard threshold voltage MOS devices as compared with high threshold voltage MOS devices may have improved speed performance, but greater leakage current. Likewise, a flip-flop operating with high threshold voltage MOS devices may reduce the leakage current and have better power efficiency, but decreased speed and performance. An optimized flip-flop may include a combination of standard threshold voltage MOS devices and high threshold voltage MOS devices. The optimized flip-flop may have less leakage during stand-by mode as compared to a flip-flop with standard threshold voltage MOS devices. In addition, the optimized flip-flop may have better performance and speed as compared to a flip-flop with high threshold voltage MOS devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.