Test coverage of integrated circuits with masking pattern selection
US8856720B2 · kind B2 · utility
9Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2013 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jan 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.