Method for improving device performance using dual stress liner boundary
US8859357B2 · kind B2 · utility
6Cited by
0References
9Claims
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Key dates
| Filing date | Nov 3, 2011 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Jun 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
Abstract
An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.