Memory transistor with multiple charge storing layers and a high work function gate electrode
US8859374B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2011 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Oct 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method comprises: (i) forming an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate in at least a first region in which a non-volatile memory transistor is to be formed, the ONO dielectric stack including a multi-layer charge storage layer; (ii) forming an oxide layer on the surface of the substrate in a second region in which a metal oxide semiconductor (MOS) logic transistor is to be formed; and (iii) forming a high work function gate electrode on a surface of the ONO dielectric stack. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.