Resistive memory device and fabrication method thereof
US8860003B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 2013 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Mar 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/82
Abstract
A resistive memory device capable of implementing a multi-level cell (MLC) and a fabrication method thereof are provided. The resistive memory device includes a lower electrode connected to a switching device and including a first node and a second node formed on a top thereof to be spaced at a fixed interval, a phase-change material pattern formed on the first node and the second node, an upper electrode formed on the phase-change material pattern, a conductive material layer formed on a top and outer sidewall of the upper electrode, a first contact plug formed on one edge of the upper electrode to be connected to the upper electrode and the conductive material layer, and a second contact plug formed on the other edge of the upper electrode to be connected to the upper electrode and the conductive material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.