FinFET-compatible metal-insulator-metal capacitor
US8860107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2010 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Jul 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
At least one semiconductor fin for a capacitor is formed concurrently with other semiconductor fins for field effect transistors. A lower conductive layer is deposited and lithographically patterned to form a lower conductive plate located on the at least one semiconductor fin. A dielectric layer and at least one upper conductive layer are formed and lithographically patterned to form a node dielectric and an upper conductive plate over the lower conductive plate as well as a gate dielectric and a gate conductor over the other semiconductor fins. The lower conductive plate, the node dielectric, and the upper conductive plate collectively form a capacitor. The finFETs may be dual gate finFETs or trigate finFETs. A buried insulator layer may be optionally recessed to increase the capacitance. Alternately, the lower conductive plate may be formed on a planar surface of the buried insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.