Nonvolatile charge trap memory device having a high dielectric constant blocking region
US8860122B1 · kind B1 · utility
32Cited by
7References
11Claims
0Family size
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Key dates
| Filing date | May 24, 2011 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | May 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/00
Abstract
A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. The gate stack includes a high dielectric constant blocking region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.