Multi-die processor
US8860199B2 · kind B2 · utility
35Cited by
8References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2009 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Jul 16, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.