Techniques for wafer-level processing of QFN packages
US8860222B2 · kind B2 · utility
1Cited by
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11Claims
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Key dates
| Filing date | Nov 30, 2012 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Dec 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.