Clock multiplexer
US8860468B1 · kind B1 · utility
8Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2013 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Jul 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock multiplexer includes first and second input stages for outputting first and second clock signals, respectively. The first and second input stages each include a flip-flop, a latch and a first logic gate. Reset terminals of the flip-flops receive a select signal based on which the first and second input stages output the first and second clock signals. A second logic gate is connected to the first and second input stages for selectively providing the first and second clock signals as an output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.