Clocked memory with latching predecoder circuitry
US8861301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2012 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Oct 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.