Method and apparatus for performing lossy integer multiplier synthesis
US8862652B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2012 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Mar 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5318
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for deriving an RTL a logic circuit performing a multiplication as the sum of addends operation with a desired rounding position. In this, an error requirement to meet for the design rounding position is derived. For each of the CCT and the VCT implementation a number columns to discard is derived and a constant to include in the sum addends. For an LMS implementation, a number of columns to discard is derived. After discarding the columns and including the constants as appropriate, an RTL representation of the sum of addends operation is derived for each of the CCT, VCT and LMS implementations and a logic circuit synthesized for each of these. The logic circuit which gives the best implementation is selected for manufacture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.