Processor supporting coarse-grained array and VLIW modes
US8862825B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2011 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | May 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and an operating method are described. By diversifying an L1 memory being accessed, based on an execution mode of the processor, an operating performance of the processor may be enhanced. By disposing a local/stack section in a system dynamic random access memory (DRAM) located external to the processor, a size of a scratch pad memory may be reduced without deteriorating a performance. While a core of the processor is performing in a very long instruction word (VLIW) mode, the core may data-access a cache memory and thus, a bottleneck may not occur with respect to the scratch pad memory even though a memory access occurs with respect to the scratch pad memory by an external component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.