Memory testing with selective use of an error correction code decoder
US8862953B2 · kind B2 · utility
12Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2013 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Apr 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes directing an access of a memory location of a memory device to an error correction code (ECC) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location. The method further includes determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.